1. Field of the Invention
The present invention relates to buffer circuits and, particularly, to a buffer circuit which does not allow a current to flow inside a terminal even when a voltage higher than a power supply voltage is input from outside of the terminal.
2. Description of Related Art
Recent semiconductor apparatus have multiple functions, and enormous variety of input/output signals are used. At the same time, the semiconductor apparatus are required to have as small number of terminals as possible. A recently adopted approach to meet this requirement is to use one terminal in both input mode and output mode. Meanwhile, in order to reduce power consumption, a recent technique operates a semiconductor apparatus and the semiconductor apparatus mounted in electronic equipment by using a plurality of power systems corresponding to their functions, e.g. 3.3V power system and 5.0V power system, thereby operating one electronic equipment. In such electronic equipment, when a signal is input from the 5.0V power system to the semiconductor apparatus of 3.3V power system, a current flows undesirably inside the semiconductor apparatus of 3.3V power system. In order to overcome this drawback, a buffer circuit (tolerant buffer circuit) which prevents a current from flowing inside a terminal upon input of a voltage higher than a power supply voltage may be used. For example, the buffer circuit which operates with the 3.3V power system outputs a signal with an amplitude ranging from the ground to 3.3V in the output mode. In the input mode, on the other hand, the buffer circuit receives a signal, setting its terminal at a high impedance state. Further, when the 3.3V system buffer circuit receives an input from the semiconductor apparatus of 5.0V power system, it can receive a signal with an amplitude ranging from the ground to 5.0V while preventing a current from flowing inside a terminal. An example of such a buffer circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2004-328443.
FIG. 12 shows a typical buffer circuit 1200 in a related art. A typical buffer circuit 1200 of a related art is described herein with reference to FIG. 12. The buffer circuit 1200 is in the output mode when an OEB signal is at Low level (e.g. ground voltage) and in the input mode when it is at High level (e.g. power supply voltage).
The operation of the buffer circuit 1200 in the output mode is as follows. When the OEB signal is at Low level, the buffer circuit 1200 outputs a signal of the same logic as an input DATA signal from an output stage 1201.
The operation of the buffer circuit 1200 in the input mode is as follows. When the OEB signal is at High level, the buffer circuit 1200 sets an OUTP signal at Low level and OUTN signal at High level regardless of the state of the DATA signal. A PMOS transistor P1 and an NMOS transistor N1 in the output stage 1201 thereby become nonconductive. The node 1 of the output stage 1201 thus enters a high impedance state, so that an input buffer 1208 receives the signal.
In some cases, a signal having an amplitude of an external power supply voltage which is higher than a power supply voltage VDD is input as an input voltage. In order to prevent a current from flowing inside in this case, the buffer circuit 1200 has a gate controller 1206 and a transfer gate 1204.
The gate controller 1206 sets the gate voltage of the PMOS transistor P1 at an external power supply voltage upon input of the external power supply voltage, thereby preventing the PMOS transistor P1 from becoming conductive.
The transfer gate 1204 avoids that an external power supply voltage is applied to a pre-driver 1202 upon input of the external power supply voltage. This prevents backflow current to the power supply voltage VDD which is connected to the pre-driver 1202.
The buffer circuit 1200, however, needs to delay the timing for switching the transfer gate 1204 into the nonconductive state by using a delay circuit when switching between the input and output modes in order to set the PMOS transistor P1 absolutely nonconductive. It is thus required to design a delay circuit for making a delay time and adjust the timing.
In addition, it is necessary in the transfer gate 1204 to have a large transistor size in order to reduce a parasitic resistance of the transistor, which causes an increase in the size of a semiconductor apparatus. Further, the rise of the signal at the PMOS transistor P1 is slow due to the parasitic resistance of the transistor of the transfer gate 1204, which causes a limitation in operation speed.